/*
 * Copyright (C) 2019 Unigroup Spreadtrum & RDA Technologies Co., Ltd.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 * updated at 2019-02-11 15:07:05
 *
 */


#ifndef ANLG_PHY_G11_H
#define ANLG_PHY_G11_H

#define CTL_BASE_ANLG_PHY_G11 0x63530000


#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_4L_TXCLKLANE          ( CTL_BASE_ANLG_PHY_G11 + 0x0000 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_4L_TXDATA_0           ( CTL_BASE_ANLG_PHY_G11 + 0x0004 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_4L_TXDATA_1           ( CTL_BASE_ANLG_PHY_G11 + 0x0008 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_4L_TXDATA_2           ( CTL_BASE_ANLG_PHY_G11 + 0x000C )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_4L_TXDATA_3           ( CTL_BASE_ANLG_PHY_G11 + 0x0010 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_4L_TXDATAESC          ( CTL_BASE_ANLG_PHY_G11 + 0x0014 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_4L_STATE_RX           ( CTL_BASE_ANLG_PHY_G11 + 0x0018 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_4L_ERR                ( CTL_BASE_ANLG_PHY_G11 + 0x001C )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_4L_CTRL               ( CTL_BASE_ANLG_PHY_G11 + 0x0020 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_4L_RSVD               ( CTL_BASE_ANLG_PHY_G11 + 0x0024 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_4L_TEST               ( CTL_BASE_ANLG_PHY_G11 + 0x0028 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_4L_DATALANE_CTRL      ( CTL_BASE_ANLG_PHY_G11 + 0x002C )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_DUMY_CTRL             ( CTL_BASE_ANLG_PHY_G11 + 0x0030 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_MIPI_CTRL7                ( CTL_BASE_ANLG_PHY_G11 + 0x0034 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_REG_SEL_CFG_0             ( CTL_BASE_ANLG_PHY_G11 + 0x0038 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_REG_SEL_CFG_1             ( CTL_BASE_ANLG_PHY_G11 + 0x003C )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_4L_TXCLKLANE          ( CTL_BASE_ANLG_PHY_G11 + 0x0040 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_4L_TXDATA_0           ( CTL_BASE_ANLG_PHY_G11 + 0x0044 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_4L_TXDATA_1           ( CTL_BASE_ANLG_PHY_G11 + 0x0048 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_4L_TXDATA_2           ( CTL_BASE_ANLG_PHY_G11 + 0x004C )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_4L_TXDATA_3           ( CTL_BASE_ANLG_PHY_G11 + 0x0050 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_4L_TXDATAESC          ( CTL_BASE_ANLG_PHY_G11 + 0x0054 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_4L_STATE_RX           ( CTL_BASE_ANLG_PHY_G11 + 0x0058 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_4L_ERR                ( CTL_BASE_ANLG_PHY_G11 + 0x005C )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_4L_CTRL               ( CTL_BASE_ANLG_PHY_G11 + 0x0060 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_4L_RSVD               ( CTL_BASE_ANLG_PHY_G11 + 0x0064 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_4L_TEST               ( CTL_BASE_ANLG_PHY_G11 + 0x0068 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_4L_DATALANE_CTRL      ( CTL_BASE_ANLG_PHY_G11 + 0x006C )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_DUMY_CTRL             ( CTL_BASE_ANLG_PHY_G11 + 0x0070 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_MIPI_CTRL7                ( CTL_BASE_ANLG_PHY_G11 + 0x0074 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_REG_SEL_CFG_0             ( CTL_BASE_ANLG_PHY_G11 + 0x0078 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_REG_SEL_CFG_1             ( CTL_BASE_ANLG_PHY_G11 + 0x007C )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_4L_TXCLKLANE          ( CTL_BASE_ANLG_PHY_G11 + 0x0080 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_4L_TXDATA_0           ( CTL_BASE_ANLG_PHY_G11 + 0x0084 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_4L_TXDATA_1           ( CTL_BASE_ANLG_PHY_G11 + 0x0088 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_4L_TXDATA_2           ( CTL_BASE_ANLG_PHY_G11 + 0x008C )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_4L_TXDATA_3           ( CTL_BASE_ANLG_PHY_G11 + 0x0090 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_4L_TXDATAESC          ( CTL_BASE_ANLG_PHY_G11 + 0x0094 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_4L_STATE_RX           ( CTL_BASE_ANLG_PHY_G11 + 0x0098 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_4L_ERR                ( CTL_BASE_ANLG_PHY_G11 + 0x009C )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_4L_CTRL               ( CTL_BASE_ANLG_PHY_G11 + 0x00A0 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_4L_RSVD               ( CTL_BASE_ANLG_PHY_G11 + 0x00A4 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_4L_TEST               ( CTL_BASE_ANLG_PHY_G11 + 0x00A8 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_4L_DATALANE_CTRL      ( CTL_BASE_ANLG_PHY_G11 + 0x00AC )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_DUMY_CTRL             ( CTL_BASE_ANLG_PHY_G11 + 0x00B0 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_MIPI_CTRL7                ( CTL_BASE_ANLG_PHY_G11 + 0x00B4 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_REG_SEL_CFG_0             ( CTL_BASE_ANLG_PHY_G11 + 0x00B8 )
#define REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_REG_SEL_CFG_1             ( CTL_BASE_ANLG_PHY_G11 + 0x00BC )

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_4L_TXCLKLANE */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXREQUESTHSCLK             BIT(4)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXULPSCLK                  BIT(3)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXULPSEXITCLK              BIT(2)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_STOPSTATECLK               BIT(1)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_ULPSACTIVENOTCLK           BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_4L_TXDATA_0 */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXREQUESTDATAHS_0          BIT(10)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXREQUESTESC_0             BIT(9)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXLPDTESC_0                BIT(8)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXULPSESC_0                BIT(7)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXULPSEXIT_0               BIT(6)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXTRIGGERESC_0(x)          (((x) & 0xF) << 2)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXVALIDESC_0               BIT(1)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXREADYESC_0               BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_4L_TXDATA_1 */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXREQUESTDATAHS_1          BIT(10)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXREQUESTESC_1             BIT(9)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXLPDTESC_1                BIT(8)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXULPSESC_1                BIT(7)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXULPSEXIT_1               BIT(6)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXTRIGGERESC_1(x)          (((x) & 0xF) << 2)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXVALIDESC_1               BIT(1)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXREADYESC_1               BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_4L_TXDATA_2 */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXREQUESTDATAHS_2          BIT(10)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXREQUESTESC_2             BIT(9)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXLPDTESC_2                BIT(8)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXULPSESC_2                BIT(7)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXULPSEXIT_2               BIT(6)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXTRIGGERESC_2(x)          (((x) & 0xF) << 2)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXVALIDESC_2               BIT(1)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXREADYESC_2               BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_4L_TXDATA_3 */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXREQUESTDATAHS_3          BIT(10)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXREQUESTESC_3             BIT(9)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXLPDTESC_3                BIT(8)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXULPSESC_3                BIT(7)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXULPSEXIT_3               BIT(6)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXTRIGGERESC_3(x)          (((x) & 0xF) << 2)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXVALIDESC_3               BIT(1)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXREADYESC_3               BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_4L_TXDATAESC */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXDATAESC_0(x)             (((x) & 0xFF) << 24)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXDATAESC_1(x)             (((x) & 0xFF) << 16)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXDATAESC_2(x)             (((x) & 0xFF) << 8)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXDATAESC_3(x)             (((x) & 0xFF))

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_4L_STATE_RX */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_RXCLKESC_0                 BIT(27)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_RXCLKESC_1                 BIT(26)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_RXCLKESC_2                 BIT(25)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_RXCLKESC_3                 BIT(24)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_RXLPDTESC_0                BIT(23)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_RXTRIGGERESC_0(x)          (((x) & 0xF) << 19)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_RXVALIDESC_0               BIT(18)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_RXLPDTESC_1                BIT(17)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_RXTRIGGERESC_1(x)          (((x) & 0xF) << 13)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_RXVALIDESC_1               BIT(12)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_RXLPDTESC_2                BIT(11)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_RXTRIGGERESC_2(x)          (((x) & 0xF) << 7)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_RXVALIDESC_2               BIT(6)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_RXLPDTESC_3                BIT(5)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_RXTRIGGERESC_3(x)          (((x) & 0xF) << 1)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_RXVALIDESC_3               BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_4L_ERR */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_ERRESC_0                   BIT(19)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_ERRSYNCESC_0               BIT(18)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_ERRCONTROL_0               BIT(17)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_ERRCONTENTIONLP0_0         BIT(16)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_ERRCONTENTIONLP1_0         BIT(15)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_ERRESC_1                   BIT(14)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_ERRSYNCESC_1               BIT(13)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_ERRCONTROL_1               BIT(12)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_ERRCONTENTIONLP0_1         BIT(11)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_ERRCONTENTIONLP1_1         BIT(10)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_ERRESC_2                   BIT(9)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_ERRSYNCESC_2               BIT(8)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_ERRCONTROL_2               BIT(7)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_ERRCONTENTIONLP0_2         BIT(6)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_ERRCONTENTIONLP1_2         BIT(5)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_ERRESC_3                   BIT(4)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_ERRSYNCESC_3               BIT(3)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_ERRCONTROL_3               BIT(2)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_ERRCONTENTIONLP0_3         BIT(1)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_ERRCONTENTIONLP1_3         BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_4L_CTRL */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_PS_PD_S                    BIT(21)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_PS_PD_L                    BIT(20)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_SHUTDOWNZ                  BIT(19)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_RSTZ                       BIT(18)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_ENABLE_0                   BIT(17)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_ENABLE_1                   BIT(16)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_ENABLE_2                   BIT(15)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_ENABLE_3                   BIT(14)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_ENABLECLK                  BIT(13)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_FORCEPLL                   BIT(12)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_PLLLOCK                    BIT(11)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_BISTON                     BIT(10)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_BISTDONE                   BIT(9)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_IF_SEL                     BIT(8)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TRIMBG(x)                  (((x) & 0xF) << 4)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TX_RCTL(x)                 (((x) & 0xF))

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_4L_RSVD */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_RESERVED(x)                (((x) & 0xFF) << 8)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_RESERVEDO(x)               (((x) & 0xFF))

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_4L_TEST */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TESTDIN(x)                 (((x) & 0xFF) << 11)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TESTDOUT(x)                (((x) & 0xFF) << 3)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TESTEN                     BIT(2)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TESTCLK                    BIT(1)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TESTCLR                    BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_4L_DATALANE_CTRL */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TURNREQUEST_0              BIT(22)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_DIRECTION_0                BIT(21)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TURNDISABLE_0              BIT(20)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_FORCERXMODE_0              BIT(19)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_FORCETXSTOPMODE_0          BIT(18)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_STOPSTATEDATA_0            BIT(17)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TURNREQUEST_1              BIT(16)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TURNDISABLE_1              BIT(15)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_FORCERXMODE_1              BIT(14)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_FORCETXSTOPMODE_1          BIT(13)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_STOPSTATEDATA_1            BIT(12)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TURNREQUEST_2              BIT(11)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_DIRECTION_2                BIT(10)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TURNDISABLE_2              BIT(9)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_FORCERXMODE_2              BIT(8)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_FORCETXSTOPMODE_2          BIT(7)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_STOPSTATEDATA_2            BIT(6)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TURNREQUEST_3              BIT(5)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_DIRECTION_3                BIT(4)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TURNDISABLE_3              BIT(3)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_FORCERXMODE_3              BIT(2)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_FORCETXSTOPMODE_3          BIT(1)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_STOPSTATEDATA_3            BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_DUMY_CTRL */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_ANALOG_DSI_DUMY_IN(x)          (((x) & 0xFFFF) << 16)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_ANALOG_DSI_DUMY_OUT(x)         (((x) & 0xFFFF))

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_MIPI_CTRL7 */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_ISO_SW_EN                  BIT(4)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXSKEWCALHS_0              BIT(3)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXSKEWCALHS_1              BIT(2)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXSKEWCALHS_2              BIT(1)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_DSI_TXSKEWCALHS_3              BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_REG_SEL_CFG_0 */

#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_TXREQUESTHSCLK     BIT(31)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_TXULPSCLK          BIT(30)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_TXULPSEXITCLK      BIT(29)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_TXREQUESTDATAHS_0  BIT(28)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_TXREQUESTESC_0     BIT(27)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_TXLPDTESC_0        BIT(26)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_TXULPSESC_0        BIT(25)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_TXULPSEXIT_0       BIT(24)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_TXTRIGGERESC_0     BIT(23)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_TXVALIDESC_0       BIT(22)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_TXREQUESTDATAHS_1  BIT(21)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_TXREQUESTESC_1     BIT(20)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_TXULPSESC_1        BIT(19)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_TXULPSEXIT_1       BIT(18)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_TXREQUESTDATAHS_2  BIT(17)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_TXREQUESTESC_2     BIT(16)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_TXULPSESC_2        BIT(15)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_TXULPSEXIT_2       BIT(14)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_TXREQUESTDATAHS_3  BIT(13)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_TXREQUESTESC_3     BIT(12)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_TXULPSESC_3        BIT(11)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_TXULPSEXIT_3       BIT(10)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_TXDATAESC_0        BIT(9)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_PS_PD_S            BIT(8)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_PS_PD_L            BIT(7)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_SHUTDOWNZ          BIT(6)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_RSTZ               BIT(5)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_ENABLE_0           BIT(4)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_ENABLE_1           BIT(3)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_ENABLE_2           BIT(2)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_ENABLE_3           BIT(1)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_ENABLECLK          BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_0_REG_SEL_CFG_1 */

#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_FORCEPLL           BIT(10)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_TESTDIN            BIT(9)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_TESTEN             BIT(8)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_TESTCLK            BIT(7)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_TESTCLR            BIT(6)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_TURNREQUEST_0      BIT(5)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_ISO_SW_EN          BIT(4)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_TXSKEWCALHS_0      BIT(3)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_TXSKEWCALHS_1      BIT(2)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_TXSKEWCALHS_2      BIT(1)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_0_DSI_TXSKEWCALHS_3      BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_4L_TXCLKLANE */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXREQUESTHSCLK             BIT(4)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXULPSCLK                  BIT(3)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXULPSEXITCLK              BIT(2)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_STOPSTATECLK               BIT(1)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_ULPSACTIVENOTCLK           BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_4L_TXDATA_0 */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXREQUESTDATAHS_0          BIT(10)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXREQUESTESC_0             BIT(9)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXLPDTESC_0                BIT(8)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXULPSESC_0                BIT(7)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXULPSEXIT_0               BIT(6)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXTRIGGERESC_0(x)          (((x) & 0xF) << 2)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXVALIDESC_0               BIT(1)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXREADYESC_0               BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_4L_TXDATA_1 */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXREQUESTDATAHS_1          BIT(10)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXREQUESTESC_1             BIT(9)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXLPDTESC_1                BIT(8)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXULPSESC_1                BIT(7)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXULPSEXIT_1               BIT(6)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXTRIGGERESC_1(x)          (((x) & 0xF) << 2)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXVALIDESC_1               BIT(1)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXREADYESC_1               BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_4L_TXDATA_2 */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXREQUESTDATAHS_2          BIT(10)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXREQUESTESC_2             BIT(9)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXLPDTESC_2                BIT(8)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXULPSESC_2                BIT(7)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXULPSEXIT_2               BIT(6)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXTRIGGERESC_2(x)          (((x) & 0xF) << 2)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXVALIDESC_2               BIT(1)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXREADYESC_2               BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_4L_TXDATA_3 */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXREQUESTDATAHS_3          BIT(10)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXREQUESTESC_3             BIT(9)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXLPDTESC_3                BIT(8)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXULPSESC_3                BIT(7)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXULPSEXIT_3               BIT(6)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXTRIGGERESC_3(x)          (((x) & 0xF) << 2)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXVALIDESC_3               BIT(1)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXREADYESC_3               BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_4L_TXDATAESC */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXDATAESC_0(x)             (((x) & 0xFF) << 24)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXDATAESC_1(x)             (((x) & 0xFF) << 16)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXDATAESC_2(x)             (((x) & 0xFF) << 8)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXDATAESC_3(x)             (((x) & 0xFF))

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_4L_STATE_RX */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_RXCLKESC_0                 BIT(27)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_RXCLKESC_1                 BIT(26)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_RXCLKESC_2                 BIT(25)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_RXCLKESC_3                 BIT(24)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_RXLPDTESC_0                BIT(23)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_RXTRIGGERESC_0(x)          (((x) & 0xF) << 19)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_RXVALIDESC_0               BIT(18)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_RXLPDTESC_1                BIT(17)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_RXTRIGGERESC_1(x)          (((x) & 0xF) << 13)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_RXVALIDESC_1               BIT(12)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_RXLPDTESC_2                BIT(11)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_RXTRIGGERESC_2(x)          (((x) & 0xF) << 7)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_RXVALIDESC_2               BIT(6)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_RXLPDTESC_3                BIT(5)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_RXTRIGGERESC_3(x)          (((x) & 0xF) << 1)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_RXVALIDESC_3               BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_4L_ERR */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_ERRESC_0                   BIT(19)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_ERRSYNCESC_0               BIT(18)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_ERRCONTROL_0               BIT(17)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_ERRCONTENTIONLP0_0         BIT(16)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_ERRCONTENTIONLP1_0         BIT(15)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_ERRESC_1                   BIT(14)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_ERRSYNCESC_1               BIT(13)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_ERRCONTROL_1               BIT(12)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_ERRCONTENTIONLP0_1         BIT(11)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_ERRCONTENTIONLP1_1         BIT(10)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_ERRESC_2                   BIT(9)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_ERRSYNCESC_2               BIT(8)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_ERRCONTROL_2               BIT(7)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_ERRCONTENTIONLP0_2         BIT(6)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_ERRCONTENTIONLP1_2         BIT(5)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_ERRESC_3                   BIT(4)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_ERRSYNCESC_3               BIT(3)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_ERRCONTROL_3               BIT(2)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_ERRCONTENTIONLP0_3         BIT(1)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_ERRCONTENTIONLP1_3         BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_4L_CTRL */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_PS_PD_S                    BIT(21)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_PS_PD_L                    BIT(20)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_SHUTDOWNZ                  BIT(19)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_RSTZ                       BIT(18)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_ENABLE_0                   BIT(17)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_ENABLE_1                   BIT(16)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_ENABLE_2                   BIT(15)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_ENABLE_3                   BIT(14)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_ENABLECLK                  BIT(13)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_FORCEPLL                   BIT(12)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_PLLLOCK                    BIT(11)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_BISTON                     BIT(10)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_BISTDONE                   BIT(9)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_IF_SEL                     BIT(8)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TRIMBG(x)                  (((x) & 0xF) << 4)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TX_RCTL(x)                 (((x) & 0xF))

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_4L_RSVD */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_RESERVED(x)                (((x) & 0xFF) << 8)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_RESERVEDO(x)               (((x) & 0xFF))

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_4L_TEST */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TESTDIN(x)                 (((x) & 0xFF) << 11)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TESTDOUT(x)                (((x) & 0xFF) << 3)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TESTEN                     BIT(2)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TESTCLK                    BIT(1)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TESTCLR                    BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_4L_DATALANE_CTRL */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TURNREQUEST_0              BIT(22)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_DIRECTION_0                BIT(21)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TURNDISABLE_0              BIT(20)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_FORCERXMODE_0              BIT(19)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_FORCETXSTOPMODE_0          BIT(18)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_STOPSTATEDATA_0            BIT(17)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TURNREQUEST_1              BIT(16)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TURNDISABLE_1              BIT(15)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_FORCERXMODE_1              BIT(14)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_FORCETXSTOPMODE_1          BIT(13)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_STOPSTATEDATA_1            BIT(12)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TURNREQUEST_2              BIT(11)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_DIRECTION_2                BIT(10)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TURNDISABLE_2              BIT(9)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_FORCERXMODE_2              BIT(8)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_FORCETXSTOPMODE_2          BIT(7)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_STOPSTATEDATA_2            BIT(6)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TURNREQUEST_3              BIT(5)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_DIRECTION_3                BIT(4)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TURNDISABLE_3              BIT(3)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_FORCERXMODE_3              BIT(2)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_FORCETXSTOPMODE_3          BIT(1)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_STOPSTATEDATA_3            BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_DUMY_CTRL */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_ANALOG_DSI_DUMY_IN(x)          (((x) & 0xFFFF) << 16)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_ANALOG_DSI_DUMY_OUT(x)         (((x) & 0xFFFF))

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_MIPI_CTRL7 */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_ISO_SW_EN                  BIT(4)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXSKEWCALHS_0              BIT(3)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXSKEWCALHS_1              BIT(2)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXSKEWCALHS_2              BIT(1)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_DSI_TXSKEWCALHS_3              BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_REG_SEL_CFG_0 */

#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_TXREQUESTHSCLK     BIT(31)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_TXULPSCLK          BIT(30)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_TXULPSEXITCLK      BIT(29)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_TXREQUESTDATAHS_0  BIT(28)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_TXREQUESTESC_0     BIT(27)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_TXLPDTESC_0        BIT(26)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_TXULPSESC_0        BIT(25)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_TXULPSEXIT_0       BIT(24)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_TXTRIGGERESC_0     BIT(23)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_TXVALIDESC_0       BIT(22)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_TXREQUESTDATAHS_1  BIT(21)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_TXREQUESTESC_1     BIT(20)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_TXULPSESC_1        BIT(19)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_TXULPSEXIT_1       BIT(18)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_TXREQUESTDATAHS_2  BIT(17)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_TXREQUESTESC_2     BIT(16)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_TXULPSESC_2        BIT(15)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_TXULPSEXIT_2       BIT(14)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_TXREQUESTDATAHS_3  BIT(13)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_TXREQUESTESC_3     BIT(12)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_TXULPSESC_3        BIT(11)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_TXULPSEXIT_3       BIT(10)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_TXDATAESC_0        BIT(9)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_PS_PD_S            BIT(8)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_PS_PD_L            BIT(7)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_SHUTDOWNZ          BIT(6)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_RSTZ               BIT(5)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_ENABLE_0           BIT(4)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_ENABLE_1           BIT(3)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_ENABLE_2           BIT(2)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_ENABLE_3           BIT(1)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_ENABLECLK          BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_1_REG_SEL_CFG_1 */

#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_FORCEPLL           BIT(10)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_TESTDIN            BIT(9)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_TESTEN             BIT(8)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_TESTCLK            BIT(7)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_TESTCLR            BIT(6)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_TURNREQUEST_0      BIT(5)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_ISO_SW_EN          BIT(4)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_TXSKEWCALHS_0      BIT(3)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_TXSKEWCALHS_1      BIT(2)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_TXSKEWCALHS_2      BIT(1)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_1_DSI_TXSKEWCALHS_3      BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_4L_TXCLKLANE */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXREQUESTHSCLK             BIT(4)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXULPSCLK                  BIT(3)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXULPSEXITCLK              BIT(2)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_STOPSTATECLK               BIT(1)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_ULPSACTIVENOTCLK           BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_4L_TXDATA_0 */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXREQUESTDATAHS_0          BIT(10)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXREQUESTESC_0             BIT(9)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXLPDTESC_0                BIT(8)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXULPSESC_0                BIT(7)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXULPSEXIT_0               BIT(6)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXTRIGGERESC_0(x)          (((x) & 0xF) << 2)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXVALIDESC_0               BIT(1)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXREADYESC_0               BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_4L_TXDATA_1 */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXREQUESTDATAHS_1          BIT(10)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXREQUESTESC_1             BIT(9)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXLPDTESC_1                BIT(8)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXULPSESC_1                BIT(7)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXULPSEXIT_1               BIT(6)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXTRIGGERESC_1(x)          (((x) & 0xF) << 2)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXVALIDESC_1               BIT(1)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXREADYESC_1               BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_4L_TXDATA_2 */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXREQUESTDATAHS_2          BIT(10)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXREQUESTESC_2             BIT(9)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXLPDTESC_2                BIT(8)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXULPSESC_2                BIT(7)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXULPSEXIT_2               BIT(6)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXTRIGGERESC_2(x)          (((x) & 0xF) << 2)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXVALIDESC_2               BIT(1)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXREADYESC_2               BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_4L_TXDATA_3 */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXREQUESTDATAHS_3          BIT(10)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXREQUESTESC_3             BIT(9)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXLPDTESC_3                BIT(8)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXULPSESC_3                BIT(7)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXULPSEXIT_3               BIT(6)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXTRIGGERESC_3(x)          (((x) & 0xF) << 2)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXVALIDESC_3               BIT(1)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXREADYESC_3               BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_4L_TXDATAESC */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXDATAESC_0(x)             (((x) & 0xFF) << 24)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXDATAESC_1(x)             (((x) & 0xFF) << 16)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXDATAESC_2(x)             (((x) & 0xFF) << 8)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXDATAESC_3(x)             (((x) & 0xFF))

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_4L_STATE_RX */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_RXCLKESC_0                 BIT(27)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_RXCLKESC_1                 BIT(26)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_RXCLKESC_2                 BIT(25)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_RXCLKESC_3                 BIT(24)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_RXLPDTESC_0                BIT(23)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_RXTRIGGERESC_0(x)          (((x) & 0xF) << 19)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_RXVALIDESC_0               BIT(18)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_RXLPDTESC_1                BIT(17)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_RXTRIGGERESC_1(x)          (((x) & 0xF) << 13)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_RXVALIDESC_1               BIT(12)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_RXLPDTESC_2                BIT(11)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_RXTRIGGERESC_2(x)          (((x) & 0xF) << 7)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_RXVALIDESC_2               BIT(6)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_RXLPDTESC_3                BIT(5)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_RXTRIGGERESC_3(x)          (((x) & 0xF) << 1)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_RXVALIDESC_3               BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_4L_ERR */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_ERRESC_0                   BIT(19)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_ERRSYNCESC_0               BIT(18)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_ERRCONTROL_0               BIT(17)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_ERRCONTENTIONLP0_0         BIT(16)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_ERRCONTENTIONLP1_0         BIT(15)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_ERRESC_1                   BIT(14)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_ERRSYNCESC_1               BIT(13)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_ERRCONTROL_1               BIT(12)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_ERRCONTENTIONLP0_1         BIT(11)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_ERRCONTENTIONLP1_1         BIT(10)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_ERRESC_2                   BIT(9)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_ERRSYNCESC_2               BIT(8)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_ERRCONTROL_2               BIT(7)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_ERRCONTENTIONLP0_2         BIT(6)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_ERRCONTENTIONLP1_2         BIT(5)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_ERRESC_3                   BIT(4)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_ERRSYNCESC_3               BIT(3)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_ERRCONTROL_3               BIT(2)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_ERRCONTENTIONLP0_3         BIT(1)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_ERRCONTENTIONLP1_3         BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_4L_CTRL */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_PS_PD_S                    BIT(21)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_PS_PD_L                    BIT(20)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_SHUTDOWNZ                  BIT(19)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_RSTZ                       BIT(18)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_ENABLE_0                   BIT(17)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_ENABLE_1                   BIT(16)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_ENABLE_2                   BIT(15)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_ENABLE_3                   BIT(14)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_ENABLECLK                  BIT(13)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_FORCEPLL                   BIT(12)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_PLLLOCK                    BIT(11)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_BISTON                     BIT(10)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_BISTDONE                   BIT(9)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_IF_SEL                     BIT(8)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TRIMBG(x)                  (((x) & 0xF) << 4)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TX_RCTL(x)                 (((x) & 0xF))

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_4L_RSVD */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_RESERVED(x)                (((x) & 0xFF) << 8)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_RESERVEDO(x)               (((x) & 0xFF))

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_4L_TEST */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TESTDIN(x)                 (((x) & 0xFF) << 11)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TESTDOUT(x)                (((x) & 0xFF) << 3)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TESTEN                     BIT(2)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TESTCLK                    BIT(1)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TESTCLR                    BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_4L_DATALANE_CTRL */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TURNREQUEST_0              BIT(22)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_DIRECTION_0                BIT(21)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TURNDISABLE_0              BIT(20)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_FORCERXMODE_0              BIT(19)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_FORCETXSTOPMODE_0          BIT(18)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_STOPSTATEDATA_0            BIT(17)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TURNREQUEST_1              BIT(16)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TURNDISABLE_1              BIT(15)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_FORCERXMODE_1              BIT(14)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_FORCETXSTOPMODE_1          BIT(13)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_STOPSTATEDATA_1            BIT(12)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TURNREQUEST_2              BIT(11)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_DIRECTION_2                BIT(10)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TURNDISABLE_2              BIT(9)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_FORCERXMODE_2              BIT(8)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_FORCETXSTOPMODE_2          BIT(7)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_STOPSTATEDATA_2            BIT(6)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TURNREQUEST_3              BIT(5)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_DIRECTION_3                BIT(4)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TURNDISABLE_3              BIT(3)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_FORCERXMODE_3              BIT(2)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_FORCETXSTOPMODE_3          BIT(1)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_STOPSTATEDATA_3            BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_DUMY_CTRL */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_ANALOG_DSI_DUMY_IN(x)          (((x) & 0xFFFF) << 16)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_ANALOG_DSI_DUMY_OUT(x)         (((x) & 0xFFFF))

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_MIPI_CTRL7 */

#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_ISO_SW_EN                  BIT(4)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXSKEWCALHS_0              BIT(3)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXSKEWCALHS_1              BIT(2)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXSKEWCALHS_2              BIT(1)
#define BIT_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_DSI_TXSKEWCALHS_3              BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_REG_SEL_CFG_0 */

#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_TXREQUESTHSCLK     BIT(31)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_TXULPSCLK          BIT(30)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_TXULPSEXITCLK      BIT(29)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_TXREQUESTDATAHS_0  BIT(28)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_TXREQUESTESC_0     BIT(27)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_TXLPDTESC_0        BIT(26)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_TXULPSESC_0        BIT(25)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_TXULPSEXIT_0       BIT(24)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_TXTRIGGERESC_0     BIT(23)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_TXVALIDESC_0       BIT(22)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_TXREQUESTDATAHS_1  BIT(21)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_TXREQUESTESC_1     BIT(20)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_TXULPSESC_1        BIT(19)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_TXULPSEXIT_1       BIT(18)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_TXREQUESTDATAHS_2  BIT(17)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_TXREQUESTESC_2     BIT(16)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_TXULPSESC_2        BIT(15)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_TXULPSEXIT_2       BIT(14)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_TXREQUESTDATAHS_3  BIT(13)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_TXREQUESTESC_3     BIT(12)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_TXULPSESC_3        BIT(11)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_TXULPSEXIT_3       BIT(10)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_TXDATAESC_0        BIT(9)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_PS_PD_S            BIT(8)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_PS_PD_L            BIT(7)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_SHUTDOWNZ          BIT(6)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_RSTZ               BIT(5)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_ENABLE_0           BIT(4)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_ENABLE_1           BIT(3)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_ENABLE_2           BIT(2)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_ENABLE_3           BIT(1)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_ENABLECLK          BIT(0)

/* REG_ANLG_PHY_G11_ANALOG_MIPI_DSI_4LANE_2_REG_SEL_CFG_1 */

#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_FORCEPLL           BIT(10)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_TESTDIN            BIT(9)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_TESTEN             BIT(8)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_TESTCLK            BIT(7)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_TESTCLR            BIT(6)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_TURNREQUEST_0      BIT(5)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_ISO_SW_EN          BIT(4)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_TXSKEWCALHS_0      BIT(3)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_TXSKEWCALHS_1      BIT(2)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_TXSKEWCALHS_2      BIT(1)
#define BIT_ANLG_PHY_G11_DBG_SEL_ANALOG_MIPI_DSI_4LANE_2_DSI_TXSKEWCALHS_3      BIT(0)


#endif /* ANLG_PHY_G11_H */


